Not Applicable.
Not Applicable.
The present specification relates generally to fabrication processes for integrated circuits (ICs). More specifically, the present specification relates to a method of fabricating a transistor using interferometric lithography.
The semiconductor industry needs to manufacture integrated circuits (ICs) with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This need for large scale integration has led to a continued shrinking of the circuit dimensions and features of the devices.
The ability to reduce the sizes of structures (such as shorter gate lengths in field-effect transistors) is driven by lithographic technology which is, in turn, dependent upon the wavelength of light used to expose the photoresist. In current commercial fabrication processes, optical devices expose the photoresist using light having a wavelength of 248 nm (nanometers). Research and development laboratories are experimenting with the 193 nm wavelength to reduce the sizes of structures. Further, advanced lithographic technologies are being developed that utilize radiation having a wavelength of 157 nm and even shorter wavelengths, such as those used in Deep Ultra-Violet (DEV) and Extreme Ultra-Violet (EUV) lithography (e.g., 13 nm).
Field effect transistors, such as MOSFETs (metal oxide semiconductor field effect transistors) are widely used in integrated circuits. One application for MOSFETS is in Complementary MOS (CMOS) circuits. CMOS circuits have the advantages of low standby power, high speed, and high noise immunity.
CMOS circuits require a balanced pair of N- and P-channel enhancement-mode devices (e.g., MOSFETS) on the same chip. This is typically achieved by fabricating one device on a substrate having one polarity type (e.g., N) and another in a well doped with an opposite impurity type (e.g., P). However, conventional techniques are unable to further reduce the gate lengths and other feature sizes of the CMOS circuit. Further reduction in the gate lengths and other feature sizes is required for improved speed, density, and functionality.
Another application for MOSFETs is in nonvolatile memory integrated circuits (e.g., flash, EPROM, EEPROM, etc.). Nonvolatile memory integrated circuits are used in a wide variety of commercial and military electronic devices, including handheld telephones, radios and digital cameras. The market for these electronic devices continues to demand lower voltage, lower power consumption and decreased chip size. Also, the demand for greater functionality is driving the design rule lower, from the 0.35-0.25 micron technology of today to 0.18 micron, 0.15 micron and lower.
A conventional flash memory cell of a flash memory IC includes a tunnel oxide layer disposed over a silicon substrate. The memory cell further includes a first polysilicon layer, an interpoly dielectric layer, a second polysilicon layer, a silicide layer, and sidewall spacers. In operation, a data element is stored on the first polysilicon layer, also called the floating gate. Access to the data element is obtained via the second polysilicon layer, also called the control gate or wordline. While the voltage of the data element is typically on the order of 3.3 Volts, the voltage that must be applied to the control gate to access this data element is on the order of 9 Volts. Thus, a charge pump is located on the flash memory IC to raise the chip voltage from 3.3 Volts to a target voltage of 9 Volts.
MOSFETs have been fabricated using interferometric lithography to achieve a smaller critical dimension (CD). Conventional interferometric lithography is able to achieve a CD of xcex/4, where xcex is the wavelength of the light source. In conventional interferometric lithography, a coherent laser light is split using a beam splitter. Mirrors redirect the split laser light to form an interference pattern on a layer of photoresist on a substrate. Interference in the light causes a one-dimensional grating pattern having the improved CD. No mask is used in this process.
The CD achieved with conventional interferometric lithography is still limited by the wavelength of the light used. A further reduction in feature sizes beyond that currently available with conventional interferometric lithography is required. Furthermore, the conventional process utilizes complex and costly equipment including a beam splitter and mirrors.
Accordingly, what is needed is an improved interferometric lithography technique for the fabrication of devices on an integrated circuit. Further, what is needed is a lithographic method that fabricates gates having a smaller gate width than using conventional techniques. Further still, what is needed is a system and method for interferometric lithography that requires less complex and less costly equipment. Further yet, what is needed is a system and method of interferometric lithography suitable for CMOS circuits, flash memory cells, and/or other devices. The teachings hereinbelow extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
According to one exemplary embodiment, an interferometric lithography method includes providing a first layer of material over a substrate and providing a second layer of material over the first layer of material. The method further includes providing a layer of photoresist over the first and second layers of material and providing coherent light to the first and second layers. The coherent light has an intensity insufficient to chemically transform the photoresist. The coherent light reflects off the first and second layers to interfere with an intensity sufficient to chemically transform the photoresist.
According to another exemplary embodiment, a method of fabricating features on a substrate includes providing a conductive material over a substrate and providing a sandwich comprising dielectric and reflective metal layers over the conductive material. The method further includes providing a layer of photoresist over the sandwich and exposing the layer of photoresist to a coherent light at an acute angle xcex8 with respect to the substrate. Portions of the photoresist layer are chemically transformed. The method further includes developing the photoresist layer and etching features into the conductive material layer through the developed photoresist layer.
According to yet another exemplary embodiment, a method of fabricating a grating pattern in a layer on a substrate includes providing first and second layers of material over the layer and providing a layer of photoresist over the first and second layers of material. The method further includes exposing the photoresist layer to electromagnetic radiation. The electromagnetic radiation interferes with the electromagnetic radiation reflected off the first and second layers to chemically transform the photoresist layer. The method further includes developing the photoresist layer and etching the layer to form a grating pattern in the layer.